1. Field of the Invention
The present invention generally relates to circuits for computing the root-mean-square (RMS) value of an input signal, and more specifically to an explicit circuit topology that computes the time-varying RMS value of an input signal in the log domain.
2. Description of the Related Art
RMS detectors typically fall into one of two categories: explicit or implicit. Explicit RMS detectors, such as disclosed by D. Sheingold "Nonlinear Circuits Handbook," Analog Devices, Inc., pp. 398-403, 1976, square the input signal, compute its mean, and then calculate the square root. These detectors require a multiplier, an operational amplifier (op amp) and a square-root circuit. The number of components needed to implement each of these circuits reduces the accuracy of the detector. Furthermore, squaring the input signal reduces the dynamic range of the detector.
FIG. 1 is a block diagram of a known implicit RMS detector 10 such as National Semiconductor's LH0091 True RMS to DC Converter chip, 1988. The implicit detector 10 incorporates negative feedback to produce an RMS output signal V.sub.out. A rectified input voltage signal V.sub.in is applied to a logarithm (log) converter 12 which computes the log of the input signal V.sub.in. A multiplier 14 scales the log V.sub.in signal by a factor of two, which is equivalent to squaring V.sub.in. The log V.sub.in.sup.2 voltage is applied as a positive input to a summing circuit 16. The detector's output signal V.sub.out is fed back through a log converter 18 and is applied as a negative input to the summing circuit 16, which subtracts V.sub.out from log V.sub.in.sup.2 and produces a difference voltage signal V.sub.d. An exponentiator circuit 20 performs the inverse operation of the log converter 12 on the difference voltage signal. The exponentiated voltage signal V.sub.e is input to a first order low pass filter 22. To the extent that the low pass filter approximates the "mean" operation, the output voltage signal V.sub.out is the RMS of the input voltage signal V.sub.in.
By processing the input signal in the log domain, the implicit detector improves the detector's dynamic range. However, the high frequency performance of the implicit detector is limited by the negative feedback topology such that the practical bandwidth of the detector is reduced. This topology also increases the number of components, which reduces the detector's accuracy and increases its cost. Furthermore, the feedback topology limits the implicit detector to using a first order low pass filter, which may not produce an adequate frequency response for approximating the "mean" operation for some high frequency input signals.